The present invention relates to a bus control method and apparatus. More particularly, it relates to a bus control method and apparatus for a multiprocessor setup which dispenses with a bus arbiter for controlling a common bus and which affords a high reliability and permits maintenance in operation.
One of the most recent trends in information processing by a computer is the conversion from centralized processing to decentralized processing. By way of example, when the computer is divided into an OS processor for executing an operating system program, a task processor for executing users' tasks, a communication processor, etc., and a plurality of different types of programs are simultaneously run, the number of programs to be run in parallel with each processor decreases, and hence, the response rate rises.
As shown in FIG. 1, a conventional multiprocessor setup for such decentralized processing is furnished with a single bus 1 for a plurality of processors (CPUs) 11 - 1n and also requires a bus arbiter 2 for controlling the mastership of the bus 1.
However, when the single bus 1 is directly coupled to the respective CPUs, and the bus arbiter 2 is also directly connected in this manner, there is the disadvantage that the whole system becomes inoperative due to an abnormality which may occur in only one CPU or in the bus arbiter 2. As the number of processors in the system increases, the reliability of the system becomes lower. Further, since all of the processors are coupled by the same bus 1, maintenance is impossible during operation of the system.